1. Field of the Invention
The present invention is related to an electrostatic discharge (ESD) protection device and circuit thereof. More particularly, the present invention relates to an ESD protection device and circuit thereof for bypassing an ESD current with higher shunting efficiency, faster turn-on efficiency and lower power consumption.
2. Description of Related Art
As the semiconductor technology advances, the integration of the semiconductor devices are enhanced by, for example, reducing the line width and increasing the stacked layers of the semiconductor device. For example, as the scale of the metal on oxide semiconductor (MOS) device is reduced, the gate oxides has to be thinner, the channel length has to be shorter, the source/drain junction has to be shallower, and the lightly doped drain (LDD) structure has to be adopted. However, as the area and the tolerance of the integrated circuits (IC) reduce, the damage caused by the electrostatic discharge (ESD) could become a serious problem.
Conventionally, the waveform of the electrostatic discharge (ESD) has the properties of short rise time (e.g., generally between 5 ns to 15 ns) and high pulse power (e.g., generally between 1000V to 3000V). Therefore, when the integrated circuit (IC) is damaged by the ESD, the IC might get punched through or burned out suddenly.
In general, in order to resolve the problems described above, an ESD protection circuit is generally disposed between the input and output pads of the IC to protect the IC from the ESD damage by shunting the electrostatic charges of the ESD source from the IC.
FIG. 1 is a circuit diagram schematically illustrating a conventional ESD protection circuit of an IC. Referring to FIG. 1, an ESD protection circuit 100 including a gate-ground NMOS (GGNMOS) 108 is connected between two pads 104 and 106 of the IC 102. The pad 104 is connected to a voltage VDD and the pad 106 is connected to a voltage VSS. The drain of the GGNMOS 108 is connected to the pad 104 and the source, the gate and the substrate of the GGNMOS 108 are connected to the pad 106. In general, when a positive ESD voltage is suddenly applied across the pads 104 and 106, a parasitic bipolar transistor 110 (illustrates as dotted lines 110 in FIG. 1) of the GGNMOS 108 is performed to bypass the ESD current. Alternatively, when a negative ESD voltage is applied suddenly across the pads 104 and 106, a parasitic diode (illustrated as dotted lines 112 in FIG. 1, which exists everywhere in the drain/substrate junction of the integrated circuits (IC) 102 or in the ESD protection circuit 100) is forward biased and therefore is turned on to bypass the ESD current. Generally, the performance of the ESD protection circuit 100 including the GGNMOS 108 shown in FIG. 1 is not effective enough to protect the IC 102. In addition, the turn-on efficiency of the GGNMOS 108 is not fast enough.
FIG. 2A and FIG. 2B are circuit diagrams schematically illustrating another conventional ESD protection circuit of an IC. Referring to FIG. 2A and FIG. 2B, an ESD protection circuit 200 is connected between two pads 204 and 206 of the IC 202. The pad 204 is connected to a voltage VDD and the pad 206 is connected to a voltage VSS. The ESD protection circuit 200 includes a gate-ground NMOS (GGNMOS) 208, a resistor 210, a capacitor 212 and an inverter 214. The drain of the GGNMOS 208 is connected to the pad 204, the source and the gate of the GGNMOS 208 are connected to the pad 206, and the substrate of the GGNMOS 208 is connected to the output terminal of the inverter 214. The resistor 210 is connected between the pad 204 and the input of the inverter 214, and the capacitor 212 is connected between the pad 206 and the input terminal of the inverter 214. Referring to FIG. 2B, the inverter 214 may be constructed by a PMOS 214a and an NMOS 214b. The gates of the PMOS 214a and the NMOS 214b are connected to and used as the input terminal of the inverter 214, and the drains of the PMOS 214a and the NMOS 214b are connected to and used as the output terminal of the inverter 214. The sources of the PMOS 214a and the NMOS 214b are connected to the pads 204 and 206 respectively.
Referring to FIG. 2A or FIG. 2B, the resistance-capacitance (RC) constant (i.e., the resistance R of the resistor 210 and the capacitance C of the capacitor 212, wherein the rise time of the RC constant is generally between 0.1 μs to 1 μs) is generally much larger than the rise time of the ESD voltage (generally between 5 ns to 15 ns). Therefore, when a positive ESD voltage is suddenly applied across the pads 204 and 206, the input voltage V1 at the input terminal of the inverter 214 is at low level compared to the voltage VDD due to the larger RC constant. Thus, the output voltage V2 at the output terminal of the inverter 214 is at high level since the voltage V1 is inverted by the inverter 214. Accordingly, the GGNMOS 208 will function as a bipolar transistor 110 (as illustrated by the dotted lines 110 in FIG. 1) and is triggered by the high level output voltage V2 to bypass the ESD current.
Alternatively, when a negative ESD voltage is suddenly applied across the pads 104 and 106, a parasitic diode (as illustrated by the dotted lines 112 in FIG. 1, which exists everywhere in the drain/substrate junction of the integrated circuits (IC) 202 or in the ESD protection circuit 200) is forward biased and therefore is turned on to bypass the ESD current. However, as the semiconductor technology advances, the integration of the semiconductor device is enhanced and the tolerance of the semiconductor device to the ESD current is reduced, and the conventional ESD protection circuit design may not be effective in protecting the advanced semiconductor device with low tolerance to ESD current. Therefore, an ESD protection circuit with higher performance, higher shunting efficiency, faster turn-on efficiency and lower power consumption is highly desirable.